Unlike static random access memories (SRAMs) in which the information stored remains stored indefinitely at least as long as these memories remain energized, dynamic memories have the particular feature of requiring periodic refreshing of the information stored. This is so because of the stray leakage currents which discharge the storage capacitor of each memory cell (memory slot). This refreshing is conventionally performed in the course of a read/re-write cycle consequently requiring a specific phase for re-writing the data read, since reading is destructive.
Among the known memory cells of dynamic random access memory, mention may be made in particular of those containing two or three transistors and those containing a single transistor, the information in which is, moreover, destroyed by reading. The total refresh duration of a conventional random access memory whose memory cells are organized in rows and columns depends on the number of rows in the memory. Thus, those skilled in the art are aware that it is only possible to refresh one row at a time by virtue of the destructive nature of the reading of the stored information.
Now, it is especially advantageous to be able to reduce the total refresh duration so as to correspondingly decrease the period of unavailability of the memory. A known approach includes subdividing the memory into several blocks each comprising a matrix of memory cells. By then simultaneously selecting one row from each block, the refresh duration is correspondingly decreased. However, it is still only possible to select one row at a time from each block.